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CY7C194BN
256 Kb (64K x 4) Static RAM
Features
* Fast access time: 15 ns and 25 ns * Wide voltage range: 5.0V 10% (4.5V to 5.5V) * CMOS for optimum speed/power * TTL-compatible inputs and outputs * CY7C194BN is available in 24 DIP, 24 SOJ packages.
General Description [1]
The CY7C194BN is a high-performance CMOS Asynchronous SRAM organized as 64K x 4 bits that supports an asynchronous memory interface. The device features an automatic power-down feature that significantly reduces power consumption when deselected. See the Truth Table in this data sheet for a complete description of read and write modes. The CY7C194BN is available in 24 DIP, 24 SOJ package(s).
Logic Block Diagram
Input Buffer
Row Decoder
RAM Array
Sense Amps
I/Ox
CE
Column Decoder Power Down Circuit
WE OE
(7C195 only)
X
A
X
Product Portfolio
-15 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 15 80 10 -25 25 80 10 Unit ns mA mA
Notes: 1. For best-practice recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation Document #: 001-06446 Rev. **
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised February 1, 2006
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CY7C194BN
Pin Layout and Specification
CY7C194BN 24 SOJ (8 x 15 x 3.5 mm)
A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 CE GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC A5 A4 A3 A2 A1 A0 I/O3 I/O2 I/O1 I/O0 WE
CY7C194BN 24 DIP (6.6 x 31.8 x 3.5 mm)
A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 CE GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC A5 A4 A3 A2 A1 A0 I/O3 I/O2 I/O1 I/O0 WE
Document #: 001-06446 Rev. **
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CY7C194BN
Pin Description
CY7C194BN Pin AX CE I/OX NC VCC WE Input Control Input or Output - Supply Control Type Description Address Inputs. Chip Enable. Data Input/Outputs. No Connect. Pins are not internally connected to the die. Power (5.0V). Write Enable. 24 DIP 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 18, 19, 20, 21, 22, 23 11 14, 15, 16, 17 - 24 13 24 SOJ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 18, 19, 20, 21, 22, 23 11 14, 15, 16, 17 - 24 13
CY7C194BN Truth Table
CE H L L WE X H L High Z Data Out Data In I/Ox Power-Down Read Write Mode Power Standby (ISB) Active (ICC) Active (ICC)
Document #: 001-06446 Rev. **
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CY7C194BN
Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.)
Parameter TSTG TAMB VCC VIN, VOUT IOUT VESD ILU Storage Temperature Ambient Temperature with Power Applied (i.e. case temperature) Core Supply Voltage Relative to VSS DC Voltage Applied to any Pin Relative to VSS Output Short-Circuit Current Static Discharge Voltage (per MIL-STD-883, Method 3015) Latch-up Current Description Value -65 to +150 -55 to +125 -0.5 to +7.0 -0.5 to VCC + 0.5 20 > 2001 > 200 Unit C C V V mA V mA
Operating Range
Range Commercial Ambient Temperature (TA) 0C to 70C Voltage Range (VCC) 5.0V 10%
DC Electrical Characteristics[3]
15 ns Parameter VIH VIL VOH VOL ICC ISB1 Description Input HIGH Voltage Input LOW Voltage Output HIGH Voltage VCC = Min., loh = -4.0 ma Output LOW Voltage VCC = Min., lol = 8.0 ma VCC Operating Supply VCC = Max., IOUT = 0 mA, Current f = FMAX = 1 / tRC Automatic CE Power-down Current TTL Inputs Automatic CE Power-down Current CMOS Inputs Output Leakage Current Input Load Current VCC = Max., CE VIH, VIN VIH or VIN VIL, f = FMAX VCC = Max., CE VCC - 0.3v, VIN > VCC - 0.3v or VIN 0.3, f = 0, Commercial GND Vi VCC, Output Disabled GND Vi VCC Condition Min. 2.2 -0.3 2.4 - - - Max. VCC + 0.3 0.8 - 0.4 80 30 Min. 2.2 -0.5 2.4 - - - 25 ns Max. VCC + 0.3 0.8 - 0.4 80 30 Unit V V V V mA mA
ISB2
- -5 -5
10 +5 +5
- -5 -5
10 +5 +5
mA A A
IOZ IIX
Capacitance[2]
Parameter CIN COUT Description Input Capacitance Output Capacitance Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max 7 10 Unit pF
Thermal Resistance[4]
CY7C194BN Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Conditions Still Air, soldered on a 3 x 4.5 square inches, two-layer printed circuit board 24 DIP 75.69 33.80 24 SOJ 84.15 37.56 Unit C/W
Note: 2. Tested initially and after any design or process change that may affect these parameters 3. VIL(min) = -2.0V for pulse durations of less than 20 ns. 4. Test Conditions assume a transition time of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
Document #: 001-06446 Rev. **
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CY7C194BN
AC Test Loads
Output Loads
R1 VCC VCC Output C1 R2
Output Loads
for tHZOE, tHZCE & tHZWE for R3
C2
R4
(A)*
(B)*
Thevenin Equivalent
All Input Pulses
VCC
90% 90%
Output Rth
VT VSS
10% 10%
Rise Time 1 V/ns
Fall Time 1 V/ns
* including scope and jig capacitance
AC Test Conditions
Parameter C1 C2 R1 R2 R3 R4 RTH VTH Description Capacitor 1 Capacitor 2 Resistor 1 Resistor 2 Resistor 3 Resistor 4 Resistor Thevenin Voltage Thevenin Nom. 30 5 480 255 480 255 167 1.73 V Unit pF
Document #: 001-06446 Rev. **
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CY7C194BN
AC Electrical Characteristics[2, 5, 6, 7]
15 ns Parameter tRC tAA tOHA tACE tLZCE tHZCE tPU tPD tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Description Read Cycle Time Address to Data Valid Data Hold from Address Change CE to Data Valid CE to Low Z CE to High Z CE to Power-up CE to Power-down Write Cycle Time CE to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE LOW to High Z WE HIGH to Low Z Min 15 - 3 - 3 - 0 - 15 10 10 0 0 9 8 0 - 3 Max - 15 - 15 - 7 - 15 - - - - - - - - 7 - Min 25 - 3 - 3 - 0 - 25 18 20 0 0 18 10 0 3 25 ns Max - 25 - 25 - 10 - 25 - - - - - - - - 10 - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Timing Waveforms
Read Cycle No. 1[8, 9]
tRC Address tAA tOHA Data Out Previous Data Valid Data Valid
Notes: 5. At any given temperature and voltage condition, tHZCE is less than tLZCE, and tHZWE is less than tLZWE for any given device. 6. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 7. tHZCE, tHZWE are specified as in part (b) of the A/C Test Loads. Transitions are measured 200 mV from steady state voltage. 8. Device is continuously selected. CE = VIL. 9. WE is HIGH for Read Cycle.
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CY7C194BN
Timing Waveforms (continued)
Read Cycle No. 2[2, 10, 11]
tRC Address
CE t ACE OE tDOE tLZOE High Z Data Out ICC ISB tLZCE tPU 50% Data Valid tPD 50% High Z tHZOE tHZCE
V CC Current
Write Cycle No. 1 (WE Controlled)[2, 12]
t WC Address tSCE CE tAW tSA WE tSD Data In/Out Undefined
see footnotes
tHA tPWE
tHD
Undefined See Footnotes
Data-In Valid tHZWE tLZWE
Notes: 10. WE is HIGH in read cycle. 11. Address valid prior to or coincident with CE transition LOW. 12. The minimum write cycle time is the sum of tHZWE and tSD.
Document #: 001-06446 Rev. **
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CY7C194BN
Timing Waveforms (continued)
Write Cycle No. 2 (CE Controlled)[13, 14]
tWC Address tSCE CE tSA tAW tHA
WE tSD Data In/Out High Z Data-In Valid tHD High Z
Notes: 13. This cycle is CE controlled. 14. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 001-06446 Rev. **
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CY7C194BN
Ordering Information
Speed (ns) 15 25 Ordering Code CY7C194BN-15PC CY7C194BN-15VC CY7C194BN-25VC Package Diagram 51-85013 51-85030 51-85030 Package Type 24 DIP (6.6 x 31.8 x 3.5 mm) 24 SOJ (8 x 15 x 3.5 mm) 24 SOJ (8 x 15 x 3.5 mm) Power Option Standard Standard Standard Operating Range Commercial Commercial Commercial
Please contact local sales representative regarding availability of these parts.
Package Diagrams
24-lead (300-mil) SOJ (51-85030)
PIN 1 ID
12
1
DIMENSIONS IN INCHES[MM] REFERENCE JEDEC MO-088
0.291[7.39] 0.300[7.62] 0.330[8.38] 0.350[8.89]
MIN. MAX.
PACKAGE WEIGHT 0.75gms PART #
13
24
V24.3 VZ24.3
STANDARD PKG. LEAD FREE PKG.
0.597[15.16] 0.613[15.57]
SEATING PLANE
0.120[3.05] 0.140[3.55] 0.004[0.10] 0.050[1.27] TYP. 0.025[0.63] MIN. 0.013[0.33] 0.019[0.48]
0.007[0.17] 0.013[0.33] 0.262[6.65] 0.272[6.91]
51-85030-*B
24 DIP (6.6 x 31.8 x 3.5 mm) (51-85013)
51-85013-*B
All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 001-06446 Rev. ** Page 9 of 10
(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C194BN
Document History Page
Document Title: CY7C194BN 256 Kb (64K x 4) Static RAM Document Number: 001-06446 REV. ** ECN No. 424111 Issue Date See ECN Orig. of Change NXR New Data Sheet Description of Change
Document #: 001-06446 Rev. **
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